You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Makefiles.md 5.9 KiB

3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
4 years ago
3 years ago
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. ## A Brief introduction to Makefiles
  2. This is a basic demonstration of how to write simple makefiles to manage
  3. any programming projects you might be doing on redbrick (or indeed in
  4. any development environment). The keyword in the last setence is basic
  5. as it doesn\'t explain how to fully utilise make or explain properly a
  6. lot of the makefile syntax ;o)
  7. ## Make
  8. Make is a program which can be found on most UNIX systems and even in
  9. windows (Visual C++ ships with a version of Make called NMake). It is
  10. similar to shell scripting in the way it works. You run make in a
  11. directory which contains either a file called \"Makefile\" or
  12. \"makefile\" (if both files are in the directory it would seem to use
  13. \"makefile\") and it reads the file and executes the commands in the
  14. file (unless an error occurs).
  15. Sometimes you may load a proram onto your directory on redbrick only to
  16. find that it\'s just a file of the form \"blah.tar.gz\" and then unpack
  17. it and get a load of c source code files which you don\'t know how to
  18. compile or link together. This is where the packaged Makefile will come
  19. in handy. Just cd to the directory the files are in, type make and make
  20. will automatically execute the commands in the makefile for putting the
  21. source code files together into an executable (binary) file. In the
  22. following example, I use tar to unzip a tar file, then to untar it, run
  23. ls to get a file listing, then execute make to get the final file.
  24. `The prompt starts here:{58}(~/crap)% ls <cokane@enigma ZSH emacs 18:29>`\
  25. `program.tar.gz`\
  26. `The prompt starts here:{60}(~/crap)% tar -zxvf program.tar`\
  27. `foo.c`\
  28. `foo.h`\
  29. `main.c`\
  30. `makefile`\
  31. `The prompt starts here:{61}(~/crap)% ls <cokane@enigma ZSH emacs 18:30>`\
  32. `foo.c foo.h main.c makefile program.tar`\
  33. `The prompt starts here:{62}(~/crap)% make <cokane@enigma ZSH emacs 18:30>`\
  34. `gcc -c main.c`\
  35. `gcc -c foo.c`\
  36. `echo "This is makefile"`\
  37. `This is makefile`\
  38. `gcc -ansi -o program main.o foo.o`\
  39. `rm *.o`\
  40. `The prompt starts here:{63}(~/crap)% <cokane@enigma ZSH emacs 18:30>`
  41. ## How Make works
  42. Makefiles work very much like shell scripts in that they run through a
  43. series of commands executing them one at a time depending on whether
  44. certain conditions are satisfied. The two most common types of lines
  45. you\'ll see in a makefile are variable declarations and \"make
  46. instructions\" (for want of the proper actual word :o)).
  47. Variable declarations allow you to give names, or aliases, to filenames
  48. or commands so that you aren\'t always dealing with a big long string of
  49. words, when you could just use one short variable name in it\'s place,
  50. e.g.
  51. `CC=gcc`\
  52. `FLAGS=-ansi -Wall`
  53. This allows you to use the CC variable whenever you need to call the
  54. compiler (a program known as gcc) and to use the FLAGS variable whenever
  55. you want to add those particular flags to the compiler. A sample short
  56. makefile for compiling one program might be:
  57. `CC=gcc`\
  58. `FLAGS=-ansi -Wall`\
  59. `FLAG=-o`\
  60. `PROGRAM=prog`\
  61. `OBJS=main.o lib.o`
  62. `prog:`\
  63. `$(CC) $(FLAGS) $(FLAG) $(PROGRAM) $(OBJS)`
  64. The other type of line, besides variable declarations, that you will
  65. see, is the last line in the example above. Here we have a \"target\"
  66. file which we have to make. Make looks to the bits to the right of the
  67. colon to see what it has to do to \"make\" the target on the left. Now
  68. here\'s where it gets interesting, if any of the requirements on the
  69. right of the colon are themselves \"targets\" further on down in the
  70. makefile, then make will go and make them before continuing. The items
  71. on the right of the semi-colon are known as \"dependencies\" and for
  72. make to make the target on the left, it must first make the
  73. dependencies.On the following lines (which must be indented by a tab
  74. space) make gets the instructions for what to do to make the target on
  75. the left of the semi-colon.
  76. In the sample above, the target prog has no dependencies, so make goes
  77. ahead and makes prog using the instructions on the next line. Here we
  78. just use a bunch of variables which make knows to convert to their
  79. original meanings from the \$(variable_name) syntax. So once make
  80. converts the requirements for prog, it ends up with this:
  81. `gcc -ansi -Wall -o prog main.o lib.o`
  82. As you may know this is just a program and all of it\'s arguments, make
  83. then executes this as if it was a program (you can run into errors if
  84. make tries to execute something which is nonsensical). Make also prints
  85. out what it is going to execute before executing it.
  86. I will now show you a sample makefile which firstly compiles some c
  87. source code files into object files, and then links those files together
  88. to form the finished program.
  89. `# Comments are the same as in shell scripts, i.e. start a line with a # symbol`\
  90. `CC= gcc`\
  91. `LD=ld`\
  92. `CCFLAGS= -ansi -o`\
  93. `CFLAGS= -c # This flag compiles a source code file into an object (.o) file..`\
  94. `PROG= program`\
  95. `OBJECTS= main.o foo.o`
  96. `program: $(OBJECTS) # In order for program to be made, the OBJECTS targets must..`\
  97. `echo "This is makefile" # be made first...`\
  98. `$(CC) $(CCFLAGS) $(PROG) $(OBJECTS)`
  99. `main.o: main.c`\
  100. `gcc -c main.c # There is no need for variable names if you don't want them`
  101. `foo.o: foo.c`\
  102. `$(CC) $(CFLAGS) foo.c`
  103. `clean:`\
  104. `rm *.o`
  105. ## Make arguments
  106. Sometimes you will read the instructions for setting up a program that
  107. you have downloaded on a UNIX system and it will say something like
  108. \"Run make install, then run ,make BSD.\". These arguments are just
  109. names of targets within the makefile. In the above example you can see
  110. that there is a target named \"clean\" which isn\'t required in order to
  111. make the target named program, so it isn\'t called normally. To call it
  112. you have to type
  113. `make clean`
  114. from the prompt. This will make the clean target, which in this case
  115. just deletes any object files in the current directory. As you can
  116. guess, make will only by default make the first target it comes across
  117. in a makefile. Any other unnecessary targets won\'t be made.
  118. [Category:Helpdesk](/Category:Helpdesk "wikilink")